1. Field of the Invention
This invention relates to a tri-state logic circuit, and more particularly, to a tri-state logic circuit of a BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) having a power saving characteristic, a strong noise durability, a desirable driving characteristic and switching characteristic.
2. Information Disclosure statement
Generally, in the prior art BiCMOS inverter circuit as shown in FIG. 1, when the emitter electrode of an NPN bipolar transistor Q9, that is, an output node(OUT), is in a high logic state, if an input with high logic state is inputted from an input node(IN), a PMOS transistor M41 becomes non-conducting (OFF), and NMOS transistors M42,M43 become conducting (ON), thereby an NPN bipolar transistor Q9 as well as an NMOS transistor M44 having a gate electrode connected to the drain electrode of a PMOS transistor M41, and the NMOS transistor M44 having a drain electrode connected to the base electrode of an NPN bipolar transistor Q10 respectively, resulting in the NMOS transistor M44 and NPN bipolar transistor Q9 becoming non-conducting.
Thus, the voltage of a voltage source VDD is isolated from the output node(OUT) and the base electrode of a bipolar transistor Q10 is effectively connected to the output node(OUT) through the drain-source of NMOS transistor M43 which is turned on by input, thereby the electric charges in a capacitor C4 are discharged through the collector-emitter path of an NPN bipolar transistor Q10.
Where, the NMOS transistor M44 becomes non-conducting so that a large amount of current can be conducted through the collector-emitter path of the NPN bipolar transistor Q10, this discharge changes the output node(OUT) to low logic and the NPN bipolar transistor Q10 becomes also non-conducting upon discharging the electric charge charged in the capacitor C4 to some degree.
On the other hand, the output node(OUT) becomes high logic if an input with low logic is inputted from the input node(IN), where the PMOS transistor M41 becomes conducting, and the NMOS transistors M42, M43 become non-conducting.
Thus, the voltage of the voltage source VDD propagates through the drain-source electrode path of the PMOS transistor M41 so that the NPN bipolar transistor Q9 and NMOS transistor M44 become conducting, where, the NMOS transistor M43 becomes non-conducting and the NMOS transistor M44 becomes conducting so that the base electrode of the NPN bipolar transistor Q10 becomes low logic, thereby it becomes non-conducting.
Accordingly, the voltage of the voltage source VDD is applied, through the collector-emitter electrode path of the NPN bipolar transistor Q9, to the output node(OUT) and to the capacitor C4, thereby the output node(OUT) becomes high logic.
Thus, the potential difference between the collector electrode and the emitter electrode of the NPN bipolar transistor Q9 becomes approximately 0 by charging the capacitor C4 so that the very low current-flowing state is maintained at the output node(OUT) again.
Accordingly, a large amount of current is conducted through the NPN bipolar transistor with a small power consumption so that a desired driving characteristic is obtained.
FIG. 2 illustrates a prior art tri-state logic circuit utilizing a BiCMOS logic circuit which uses a bipolar transistor as a buffer.
Referring to FIG. 2, data from an input node(Data in) is applied, through an inverter I1, to one terminal of NOR gate N1, and to one terminal of NOR gate N2, directly.
A tri-state control signal is applied to the other terminals of the NOR gates N1,N2, each output terminal of which is connected to each base electrode of the NPN bipolar transistors Q11,Q12.
A voltage of a voltage source VDD is applied to the collector electrode of the transistor Q11 having an emitter electrode connected to an output node(Data out), and to a capacitor C5, and, to the collector electrode of the NPN bipolar transistor Q12 having a emitter electrode connected to ground.
In the above mentioned prior art tri-state logic circuit, although the driving characteristic of the NPN bipolar transistor is fully utilized, there are disadvantages in that the entire circuit constitution is complicated and a lot of power is consumed, because one of the two NPN bipolar transistors Q11,Q12 is continuously conducting.